1. Field of the Invention
The present invention relates to a semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and a method of manufacturing the same. For example, the present invention relates to the structure of a NAND flash memory.
2. Description of the Related Art
Conventionally, an electrically erasable and programmable read only memory (EEPROM) has been known as a non-volatile semiconductor memory. In the EEPROM, charges are injected to a charge storage layer from a channel region via a tunnel insulating film by a tunnel current. Data is read by measuring a change of electric conductivity of a MOS transistor (memory cell transistor) in accordance with an injected charge.
In a conventional EEPROM, the gate electrode of a memory cell transistor has the following structure. Specifically, a charge storage layer is formed on a semiconductor substrate with a tunnel insulating film interposed therebetween. A control gate electrode is formed on the charge storage layer with an inter-gate insulating film interposed therebetween. The control gate electrode has a multi-layer structure having the following layers in general. One is a semiconductor layer formed on the inter-gate insulating film, and another is a metal silicide layer formed on the semiconductor layer. The foregoing structure is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-116970, for example.
According to the conventional structure, the foregoing metal silicide layer is deposited on the entire surface, and thereafter, a silicon oxide film or silicon nitride film is deposited as a mask material. The mask material and the metal silicide layer are integrally processed (etched) via a lithography process and anisotropic reactive ion etching. Thus, the corner of the upper portion of the metal silicide contacting the boundary with an insulating film as the mask material becomes sharp. For this reason, according to the conventional EEPROM, if a potential difference occurs between control gate electrodes of neighboring memory cell transistors, an electric field concentrates at the corner of the control gate. In particular, when the data is written into the selected memory cell, a voltage of 15V or more and 30V or less is applied to a control gate line connected to the selected memory cell. Moreover, 0V is applied to the neighboring control gate line to prevent a write error. As a result, there is a possibility that a breakdown voltage fault occurs between control gate electrodes of neighboring memory cells.